1. Field of the Invention
The present invention relates to methods for obtaining silicon-on-insulator structures, and more particularly to a method for forming defect-free silicon epitaxially and forming an insulating layer below the epitaxial silicon.
2. Brief Description of the Prior Art
U.S. Pat. No. 3,345,222 issued Oct. 3, 1967, to Nomura et al, and entitled METHOD OF FORMING A SEMICONDUCTOR DEVICE BY ETCHING AND EPITAXIAL DEPOSITION discloses a method for forming a semiconductor by placing a semiconductor element sample such as silicon and germanium in a quartz reaction tube, etching with a vapor phase of halogenated semiconductor material and hydrogen to form an epitaxial layer of opposite conductivity to form on the semiconductor material, and finally forming a silicon dioxide coat on the surface of the semiconductor material.
U.S. Pat. No. 4,125,427, issued Nov. 14, 1978 to Chen et al and entitled METHOD OF PROCESSING A SEMICONDUCTOR discloses a method for processing a semiconductor comprising growing a first silicon dioxide layer by oxidizing the substrate, forming a silicon nitride layer over the first SiO2 layer, growing a masking oxide layer by chemical vapor deposition. A photoresist mask is then applied to selected areas of the masking oxide layer to mask the area under which the drain, source and channel areas will appear in the substrate. The unmasked areas will represent the regions on which field oxide will be grown.
U.S. Pat. No. 4,786,609, issued Nov. 22, 1988 to Chen and entitled METHOD OF FABRICATING FIELD-EFFECT TRANSISTOR UTILIZING IMPROVED GATE SIDEWALL SPACERS, discloses a method for manufacturing a semiconductor by first forming a structure in which a dielectric layer lies along the upper surface of a major doped region of a semiconductor body. A patterned insulating cover layer overlies a similarly patterned doped layer of non-monocrystalline semiconductor material lying on the dielectric layer. The cover layer is silicon nitride. If a lightly doped drain architecture is desired, a preliminary semiconductor dopant is implanted at a low dosage into selected parts of the major region using the patterned layers as an implantion mask. A further layer of insulating material is deposited onto the upper surface, and largely all of the further layer is removed except for small spacer portions adjoining the sidewalls of the doped non-monocrystalline layer. The thickness of the sidewall spacer portions is now increased by performing a heat treatment to oxidize portions of the doped layer along its sidewalls. Next, a main semiconductor dopant is implanted into selected parts of the major region to define the main S/D regions.
U.S. Pat. No. 3,607,480, issued Dec. 30, 1968 to Harrap et al and entitled PROCESS FOR ETCHING COMPOSITE LAYERED STRUCTURES INCLUDING A LAYER OF FLUORIDE-ETCHABLE SILICON NITRIDE AND A LAYER OF SILICON DIOXIDE, discloses a single step etching process wherein silicon nitride and silicon dioxide are etched at comparable rates with an aqueous etching solution containing hydrogen and fluoride ions. The structure is formed by forming a p-type diffused base region, a relatively heavily N-doped guard or isolation ring, and relatively heavily doped N-type emitter region. During these diffusion steps, a multilevel layer of silicon oxide was sequentially grown after each of the preceding diffusions.
U.S. Pat. No. 3,731,375, issued May 8, 1973 to Agusta et al and entiled MONOLITHIC INTEGRATED STRUCTURE INCLUDING FABRICATION AND PACKAGING THERFOR discloses a method of making an integrated semiconductor structure using, for example, a wafer of p-type conductivity as the starting material, preferably a monocrystalline silicon structure. An initial layer of silicon dioxide is thermally grown, and a photoresist layer is deposited onto the wafer. The desired portions are etched away by an HF solution. An N-region is formed by diffusion, and then an oxidation cycle is effected. After removing the oxide layer, a region of N type conductivity is epitaxially grown on the surface of the wafer. Another dioxide layer is formed on the surface of the epitaxially grown region either by thermal oxidation, by pyrolytic deposition, or by RF sputtering. A number of openings are formed in specific areas of the oxide layer by standard photolithographic masking and etching techniques. A second diffusion operation is performed for isolation of the active and passive devices to be formed and, if desired, to form underpass connectors.